Verification of Bit-Error Rate in Bang-Bang Clock and Data Recovery Circuits

Version 1c, 4 May 2010 High speed serial data links are expected to transmit data at very high rates with very high fidelity. Today speeds approaching 10 Gb/s are becoming common with 40 Gb/s on the horizon. Typically, a maximum bit-error rate (BER) of 10–12-10–15 is required. Verifying such a small BER with direct simulation is quite impractical. Instead, a procedure is presented that separates the deterministic and random components of the jitter, the primary cause of errors, and verifies them individually. By separating these two components, the BER can be verified in a time that is independent of the value that must be achieved. In this way it is practical to verify the extremely small BERs required of today’s designs. This methodology, though generic in nature, will be demonstrated by applying it to the key component in a high-speed link, the clock and data recovery circuit (CDR). And in particular, it will be applied to a type of CDR that is especially difficult to characterize, a bang-bang clock and data recovery circuit (BB-CDR).